The semiconductor industry continually strives to increase semiconductor device performance and density by miniaturizing the individual semiconductor components and by miniaturizing the overall semiconductor device dimensions. For example, the semiconductor device density can be increased by more densely integrating the components on the semiconductor chip. However, increasing integration densities by placing the individual circuit elements in closer proximity increases the potential for interactions between the circuit elements. Therefore, it has become necessary to include isolation structures to prevent any significant interaction between circuit elements on the same chip.
Contemporary CMOS technologies generally employ field effect transistors that are adjacent or bounded by trenches. These trenches provide isolation (shallow trench isolation or “STI”) for the semiconductor devices. However, the close proximity of each semiconductor device to an edge or corner of the trench may create parasitic leakage paths. The parasitic leakage paths result from an enhancement of the gate electric field near the trench corners. This gate electric field is enhanced by the trench corner's small radius of curvature and the proximity of the gate conductor. As a result of the enhanced gate electric field, the trench corner has a lower threshold voltage (Vt) than the planar portion of the device.
Presently known formation techniques for such trenches generally involve a wet etch, which can exacerbate the parasitic leakage problem by sharpening the trench corners and thinning the gate dielectric near the trench corner. Furthermore, present trench formation techniques generally expose the trench corners before gate electrode deposition. The exposure of trench corners will increase the sub-Vt leakage and degrade gate oxide integrity. The aforementioned problems will be hereinafter referred to collectively as “corner effects.”
Corner effects can even dominate on-currents in applications such as DRAM chips that require narrow channel widths to achieve high density. This parallel current-carrying corner effect becomes the dominant MOSFET contributor to standby current in low standby power logic applications and to leakage in DRAM cells. Furthermore, there exists concern that the enhanced electric fields due to field crowding at the trench corner may impact dielectric integrity.
Numerous techniques have been proposed to overcome the above-discussed corner effects. Commonly owned U.S. Pat. No. 5,433,794, issued Jul. 18, 1995 to Fazan et al., hereby incorporated herein by reference, and U.S. Pat. No. 5,521,422, issued May 28, 1996 to Mandelman et al., each teach forming shallow trench isolation structures wherein insulating material spacers are formed abutting the trench corners and the isolating material filling and extending above the trench. When a wet pad oxide etch is performed, the isolating material combines with the spacers to form an isolation trench having a dome- or cap-like covering the peripheral edges of the trench, which substantially overcomes the corner effects and consequential leakage between active areas on the substrate. Although the techniques taught in these patents are effective in minimizing corner effects, the techniques require additional fabrication steps, which increase the overall cost of the semiconductor component.
U.S. Pat. No. 5,436,488, issued Jul. 25, 1995 to Poon et al., teaches improving trench isolation by increasing the thickness of the gate dielectric overlying the trench corner between the substrate and gate electrode. However, the process taught in this patent also requires numerous additional fabrication steps and structures, which of course increase the overall cost of the semiconductor component.
Therefore, it would be advantageous to develop a shallow isolation trench and a technique for forming the trench that substantially eliminates the aforementioned corner effects, while using inexpensive, commercially available, widely practiced semiconductor device fabrication techniques and apparatus.